library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity geneCond is
    Port ( selCond : in  STD_LOGIC_VECTOR (2 downto 0);
           Ra : in  STD_LOGIC_VECTOR (15 downto 0);
           cond : out  STD_LOGIC);
end geneCond;

architecture Behavioral of geneCond is

begin
process (Ra,selCond)
begin 
 cond<='0';
 case selCond is 
 when "000" => If (Ra=x"0000") then cond<='1'; end if;
 when "001" => If (Ra(15)='0') then cond<='1';end if;
 when "010" => If (Ra(15)='1' OR Ra=x"0000") then cond<='1';end if;
 when "011" => cond<='1';
 when "100" => If (Ra/=x"0000") then cond<='1';end if;
 when "101" => If (Ra(15)='1') then cond<='1';end if;
 when others => If (Ra(15)='0' AND Ra/=x"0000") then cond<='1';end if;
 end case;
end process;
end Behavioral;

